View RF3165_430798.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary 0
Typical Applications * 3V CDMA Korean-PCS Handset * 3V CDMA2000/1XRTT K-PCS Handset
RF3165
3V 1700MHz LINEAR POWER AMPLIFIER MODULE
* 3V CDMA2000/1X-EV-DO K-PCS Handset * Spread-Spectrum System
Product Description
3.00
-A-B-
The RF3165 is a high-power, high-efficiency linear amplifier module specifically designed for 3V handheld systems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V IS-95/CDMA 2000 1X handheld digital cellular equipment, spread-spectrum systems, and other applications in the 1750MHz to 1780MHz band. The RF3165 has a digital control line for low power applications to lower quiescent current. The RF3165 is assembled in at 16-pin, 3mmx3mm, QFN package.
1.00 0.80
0.10 C
3.00
0.10 C
0.10 C
0.10 C
Shaded areas represent pin 1.
-C-
1.45
+0.10 -0.15
Dimensions in mm.
SEATING PLANE SCALE: NONE
0.50 TYP.
1.45
+0.10 -0.15
0.10 C 0.08 C
0.05 0.00
0.30 TYP. 0.18
0.10 M C A B
0.50 TYP. 0.30
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
Package Style: QFN, 16-Pin, 3x3
Features * Input Internally Matched@50 * Output Internally Matched
VCC1
NC
IM
IM
* 28dBm Linear Output Power * 40% Peak Linear Efficiency
12 VCC2 11 VCC2 10 VCC2
16
15
14
13
RF IN 1 GND 2 VMODE 3 Bias VREG 4
* 28dB Linear Gain * -50dBc ACPR @ 1.25MHz
9 RF OUT
Ordering Information
RF3165 RF3165PCBA-410 3V 1700MHz Linear Power Amplifier Module Fully Assembled Evaluation Board
5 NC
6 NC
7 NC
8 NC
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A0 040730
2-1
RF3165
Absolute Maximum Ratings Parameter
Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Control Voltage (VREG) Input RF Power Mode Voltage (VMODE) Operating Temperature Storage Temperature Moisture Sensitivity Level IPC/JEDEC J-STD-20
Preliminary
Rating
+8.0 +5.2 +3.9 +10 +3.9 -30 to +110 -40 to +150 MSL 2 @260
Unit
V V V dBm V C C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
High Gain Mode (VMODE Low)
Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Linear Efficiency Maximum ICC ACPR @ 1.25MHz ACPR @ 1.98MHz ACPR @ 2.25MHz Input VSWR Output VSWR Stability Noise Power
Specification Min. Typ. Max.
Unit
Condition
T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =28dBm for all parameters (unless otherwise specified).
1750 26
1780 28 -35 -40 40 460 -50 -55 -59 2:1 6:1 10:1 -138
28
MHz dB dBc dBc dBm % mA dBc dBc dBc No oscillation>-70dBc No damage At 90MHz offset. T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =2.8V, and POUT =28dBm for all parameters (unless otherwise specified).
dBm/Hz
Low Gain Mode (VMODE High)
Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Linear Efficiency ACPR @1.25MHz ACPR @ 1.98MHz ACPR @2.25MHz Maximum ICC Linear Gain Input VSWR Output VSWR Stability 1750 27 -35 -40 28 40 -50 -54 -58 130 26 2:1 6:1 10:1 1780 MHz dB dBc dBc dBm % dBc dBc dBc mA dB
18
POUT =16dBm POUT =16dBm No oscillation>-70dBc No damage
2-2
Rev A0 040730
Preliminary
Parameter
Power Supply
Supply Voltage High Gain Idle Current Low Gain Idle Current VREG Current VMODE Current RF Turn On/Off Time DC Turn On/Off Time Total Current (Power Down) VREG Low Voltage (Power Down) VREG High Voltage (Recommended) VREG High Voltage (Operational) VMODE Voltage VMODE Voltage 3.2 3.4 65 55 2 250 1.2 2 0.2 2.8 4.2 V mA mA mA uA uS uS uA V V V V V
RF3165
Specification Min. Typ. Max. Unit Condition
VMODE =low and VREG =2.8V VMODE =high and VREG =2.8V
0 2.75 2.7 0 2.0
6 40 5 0.5 2.95 3.0 0.5 3.0
High Gain Mode Low Gain Mode
Rev A0 040730
2-3
RF3165
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pkg Base Function RF IN GND VMODE VREG NC NC NC NC RF OUT VCC2 VCC2 VCC2 NC IM IM VCC1 GND Description
RF input internally matched to 50. This input is internally AC-coupled. Ground connection. For nominal operation (High Power mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency. Regulated voltage supply for amplifier bias circuit. In power down mode, both VREG and VMODE need to be LOW (<0.5V). No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. RF output. Internally AC-coupled. Output stage collector supply. Please see the schematic for required external components. Same as pin 10. Same as pin 10. No connection. Do not connect this pin to any external circuit. Interstage matching. Connect to pin 15. Interstage matching. Connect to pin 14. First stage collector supply. A 4.7F decoupling capacitor is required. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane.
Preliminary
Interface Schematic
2-4
Rev A0 040730
Preliminary
Application Schematic
L2 VCC
RF3165
10 nF
10 F
16
15
14
13
RF IN
1 2
12 L1 11 10 Bias 9 RF OUT 1 nF Place these components next to RF3165 with minimal trace length between components.
VMODE 1 nF 3 4 VREG 1 nF 5 6 7 8
L1 = 1.5nH is recommended, but any value between 1.2nH to 2.2nH may be used. L2 = 6.8nH is recommended, but any value between 4.7nH to 8.2nH may be used. L2 may not be needed if Pin 16 is not routed directly to Pins 10, 11, and 12.
Rev A0 040730
2-5
RF3165
Evaluation Board Schematic
VCC1
Preliminary
C30 4.7 F
R1 0
L2 DNI
16 J1 RF IN 50 strip 1 2 VMODE C20 4.7 F VREG C40 4.7 F C2 1 nF P1 P1-1 P1-2 1 2 3 4 5 CON5 5 3
15
14
13
12 11 10 Bias 9
L1 1.2 nH VCC2 C1 1 nF C10 22 F
4
50 strip
J2 RF OUT
6
7
8 P2
VMODE VREG GND GND GND
P2-1
1 2
VCC2 GND VCC1 GND GND
P2-3
3 4 5 CON5
2-6
Rev A0 040730
Preliminary
Electrostatic Discharge Sensitivity
RF3165
Human Body Model (HBM) Figure 3 shows the HBM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A114.
2000 V VCC1
16
15
14
13
>2000 V NC
2000 V IM
2000 V IM
2000 V RF IN 1 GND 2 1500 V VMODE 3 2000 VREG 4
12 2000 V VCC2 11 2000 V VCC2 10 750 V VCC2 9 900 V RF OUT
5
6
7
8
750 V NC
>2000 V NC
750 V NC
14 >100 V IM
Figure 3. ESD Level - Human Body Model Machine Model (MM) Figure 4 shows the MM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A115.
200 V VCC1 >300 V NC 13 200 V IM
16
15
>2000 V NC
300 V RF IN 1 GND 2 100 V VMODE 3 250 V VREG 4
12 250 V VCC2 11 250 V VCC2 10 150 V VCC2 9 50 V RF OUT
5 >300 V NC
6 200 V NC
7 200 V NC
8 >300 V NC
Figure 4. ESD Level - Machine Model
Rev A0 040730
2-7
RF3165
PCB Design Requirements
Preliminary
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 0.78 x 0.64 (mm) D = 0.64 x 1.28 (mm) E = 1.50 (mm) Sq.
Dimensions in mm.
1.50 Typ. 0.75 Typ.
Pin 16
B
Pin 1
C
B
0.50 Typ.
A A A A E D 0.75 1.00 Typ. Typ.
A B B B B
Pin 8
0.55 Typ.
0.55 Typ.
0.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
2-8
Rev A0 040730
Preliminary
RF3165
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 (mm) Typ. B = 0.38 x 0.74 (mm) Typ. C = 1.60 (mm) Sq.
Dimensions in mm.
1.50 Typ. 0.50 Typ.
Pin 16
BBBB
Pin 1
0.50 Typ.
0.55 Typ.
A A A A
C
A A A A
Pin 8
Pin 12
0.75 Typ.
1.50 Typ.
BBBB
0.75 Typ.
0.55 Typ.
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Rev A0 040730
2-9
RF3165
Preliminary
2-10
Rev A0 040730

▲Up To Search▲

Price & Availability of RF3165

	To Download RF3165 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .